1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, especially to a flash memory using memory cells in each of which a charge storage layer and a gate electrode are stacked together.
2. Description of the Related Art
A nonvolatile semiconductor memory such as a NAND-type semiconductor memory has been employed as a memory device for various kinds of electronic equipment.
Recently, memory cells are more finely designed than ever in order to increase their memory capacities and integration densities. There is a limit, however, to reduction of processing measurements and physical dimensions of the memory cells because these factors depend on the manufacturing equipment.
In the efforts of the above, a NAND-type flash memory has been suggested, with a three-dimensional structure of memory cells stacked in a vertical direction with respect to the surface of the semiconductor substrate (see Jpn. Pat. Appln. KOKAI Publication No. 10-93083, for example).
Among NAND-type flash memories, there is a type that has a structure in which memory cells each having a floating gate electrode on the side wall of a U-shaped groove formed in the semiconductor substrate are arranged (see Jpn. Pat. Appln. KOKAI Publication No. 2006-128390, for example). In such a structure, an etching process or the like has to be performed on a polysilicon film deposited on the side surface of the groove, which requires a high decree of manufacturing techniques.
For this reason, a NAND-type flash memory of a vertically-stacked type using a metal-oxide-nitride-oxide-semiconductor (MONOS) to make the process of manufacture easier.
When memory cells are designed to have a MONOS structure, select gate transistors that are formed at the same processing step as the memory cell are also completed with a MONOS structure. A select gate transistor on the upper end of the memory cell can be readily etched, and thus a charge storage layer can also be readily removed, turning the transistor into a metal-insulator-semiconductor (MIS) structure in which a threshold voltage can be easily controlled. On the other hand, for a select gate transistor on the bottom end of the memory cell, or in other words, on the semiconductor substrate side, a charge storage layer is very difficult to remove so that that the transistor remains as the MONOS structure. When such a select gate transistor is driven, the charge storage layer carries charge, which makes the threshold voltage difficult to control. In order to cut this off, a negative potential is required. Then, a negative potential generating and controlling circuit has to be added.
Furthermore, in a NAND-type flash memory, a memory cell array region and a peripheral circuit for controlling the memory cells are arranged on a single chip. When the memory cell array region is designed to have a vertical structure, a large step height is created between the top end of the memory cell array region and the top surface of the semiconductor substrate on which the peripheral transistors are formed. With such a step height, the processing of the peripheral transistors which is conducted after the formation of the memory cell array region becomes very difficult.